Integrated circuit designers have always sought the ideal semiconductor memory: a device that is randomly accessible, can be written or read very quickly, is non-volatile, but indefinitely alterable, and consumes little power. Emerging variable resistance memories increasingly offer these advantages. Programmable Conductance Random Access Memory (PCRAM) is one example of such a memory. Additionally, Magnetoresistive Random Access Memory (MRAM) technology has been increasingly viewed as offering all these advantages. Other types of variable resistance memories include polymer-based memory and chalcogenide-based memory.
A PCRAM element has a structure including a chalcogenide-based glass region incorporating a metal (or metal ions) and electrodes on either side of the glass region. Information can be stored as a digital “1” or “0” as stable resistance states. A typical chalcogenide glass used in PCRAM devices is GexSe100−x. The chalcogenide glass can also be used in conjunction with layers of Ag and/or Ag2Se. An example of a PCRAM device is described in U.S. Pat. No. 6,348,365 to Moore and Gilton. The glass region of a PCRAM element can be made less resistive upon application of a threshold voltage. This less resistive state is maintained in a non- or semi-volatile manner and is reversible by applying a reversed voltage. The resistance state of a PCRAM element can be sensed by the application of a sub-threshold voltage through the cell element.
A magnetic memory element has a structure which includes ferromagnetic layers separated by a non-magnetic barrier layer that forms a tunnel junction. An example of an MRAM device is described in U.S. Pat. No. 6,358,756 to Sandhu et al. Information can be stored as a digital “1” or a “0” as directions of magnetization vectors in these ferromagnetic layers. Magnetic vectors in one ferromagnetic layer are magnetically fixed or pinned, while the magnetic vectors of the other ferromagnetic layer are not fixed so that the magnetization direction is free to switch between “parallel” and “antiparallel” states relative to the pinned layer. In response to parallel and antiparallel states, the magnetic memory element represents two different stable resistance states, which are read by the memory circuit as either a “1” or a “0.” Passing a current through the MRAM cell enables detection of the resistance states.
As mentioned above, polymer memory, another type of variable resistance memory, utilizes a polymer-based layer having ions dispersed therein or, alternatively, the ions may be in an adjacent layer. The polymer memory element is based on polar conductive polymer molecules. The polymer layer and ions are between two electrodes such that upon application of a voltage or electric field the ions migrate toward the negative electrode, thereby changing the resistivity of the memory cell. This altered resistivity can be sensed as a memory state.
Chalcogenide memory, another type of variable resistance memory, switches resitivity states by undergoing a phase change in response to resistive heating. The two phases corresponding to the two stable resistivity states include a polycrystalline state and an amorphous state. The amorphous state is a higher resistive state, which can be read as stored data.
A problem encountered in variable resistance memory array architectures, particularly MRAM, is the generation of sneak paths. Sneak paths during read operations are most prevalent in cross-point array architectures, but exist wherever memory cells are in direct electrical contact with one another through the array. A sneak path is a parasitic path or logic flow within a system which, under certain conditions, can initiate an undesired function or inhibit a desired function. Typically, in variable resistance memory circuits the problem is exhibited when reading data from a desired cell. Other cells in electrical contact with the addressed cell provide alternate routes for current, causing a sneak path and lowering the memory circuit's resistance to potentially unreadable levels.
A typical prior art variable resistance memory array 10, here discussed as an MRAM array, is shown in FIG. 1a. MRAM cells 12 are located and addressed at the intersecting points of bit lines 16 (also called column lines) and wordlines 18 (also called row lines). When the cell 12 to be read is addressed by grounding the wordline 18 and forcing a current on the bit line 16, the addressed cell 12 exhibits a resistivity based on its programmed state, which can be sensed by sense circuitry 14. However, parasitic current also flows through other non-addressed cells 12a of the array 10 in multiple sneak paths across the array 10. These sneak paths reduce the total resistivity of the cell 12 being sensed by the sense circuitry 14. With the diminished resistance there is a smaller margin between the programmed higher and lower resistive states of the memory cell 12, making the memory more difficult to read.
The sneak path effect on the addressed MRAM cell 12 of FIG. 1a is illustrated by the circuit diagram of FIG. 1b. As shown, the sneak path equivalent resistance 20, which is an equivalent sum of the resistances of the memory cells of the sneak path, provides an alternate route for current in the array architecture when the selected cell 12 is being sensed. Thus, the sneak path creates an effective parallel current path. In the array 10 shown in FIG. 1a, each of the bit lines 16 have an applied voltage. Thus, the entire array provides a sneak path as the memory cells 12a provide shorts between the bit lines 16 and wordlines 18. Such a sneak path makes for a relatively low resistance circuit, which makes read operations difficult. The resistance value at the bit line 16 due to sneak path influence can be described as approximately:Rsneak=R/m−1  (1)where R is the combined resistance of memory cells (e.g., 12a) and m is the total number of wordlines 18 or rows.
It would be advantageous to have a memory array architecture suitable for a variable resistance memory array that could provide similar integration characteristics as a cross-point array architecture, but which would also mitigate the detriments of sneak path occurrence.